Conventionally, memory devices have a single port with a plurality of input/output (I/O) pin sets. The single port is used for data exchange between a memory device and an external chipset. Such a memory device having the single port uses a parallel I/O interface to transmit and receive multi bit data through signal lines connected to the plurality of I/O pins. Multi-port memory arrays offer a higher data throughput compared to single-port memory arrays since more than one memory access may be performed simultaneously in a single clock cycle. However, multi-port memory array cells require more hardware (e.g., transistors, logic gates, multiplexers, etc.) per cell than single-port memory array cells.
In a conventional system including a multi-port memory array, when multiple elements are to be written to the array simultaneously, a multiplexer is associated with each storage location of the array. FIG. 1F depicts an example conventional system 170 for g data to an example data storage structure, where the example conventional system 170 rues one multiplexer 176 per storage location. The example of FIG. 1F illustrates that a multi-write register using the conventional system 170 allows for more flexibility in how a write is arranged than is necessary.